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Programa Master
Laboratory of Electronic Circuits and Systems (LCSE 1)
The knowledge of digital electronics to the practical design of a digital medium of medi-um-high complexity is applied in this course. For this, it has to be able to reach a physical implementation from functional specifications following the methodology of synchronous digi-tal circuit design.
The emphasis of the laboratory is made in the use of CAD tools to design complex digital circuits using the VHDL description hardware language. By taking advantage of this scenar-io, other important practical issues will be also covered related to the design of complex digital systems. Validation of development is an important task to be performed by simulation, as in professional environments.
Throughout the course the student has to perform several practices by applying the different phases of a classic methodology of design:
1. Study of design CAD tools
2. VHDL specification and simulation techniques
3. Synthesis and implementation over FPGA
More specifically, the goals of the course can be described as follows:
− Experience in the development of complex digital systems
− Develop the analysis ability of a specification
− Use professional tools for synthesis and digital simulation
− Understand the importance of synchronous digital systems
− Learn techniques for debugging hardware systems through simulation
− Properly plan the developing stages of a complex system
− Address all phases of development until the final test in a real FPGA
Topic 1: The VHDL
Levels of abstraction
Data types and subtypes, conversions
Constants, signals and variables, attributes
Assignments, operators
Entities, ports and generics
Architectures, concurrent sentences
Processes and sensitivity lists, sequential statements
Reuse of components, packages and libraries
Test benches, wait and after
Topic 2: Practical considerations for design and simulation-verification
State machine description
Concept synthesizable code
Synthesis common Inferences
Combinational and sequential processes
Timing and simulation
Files restrictions
Topic 3: Common mistakes in the use of VHDL
Incomplete lists sensitivity
Appearance of latches
Combinational loops
Assigning multiple signal
Use of signals and variables
Token Initialization
Practice I: consists of guided exercises with the purpose of introducing the language VHDL hardware description of and familiar with software development tools, plus the design of a small module complexity that then become part of Practice II system.
Practice II: Design of specifications for a complete digital electronic system complexity average.
The aim of the proposed practice I is to familiarize students with development tools and to dis-cover the special features of digital hardware specification through high-level languages, since it is intrinsically different from the software programming, which they are very used to.
In this sense, they are asked to hand in the answers to the issues raised in Exercises 1 through 6 as well as the generated code for Exercise 7, which will be analyzed by teachers to determine the degree of competence acquired. Then, they will meet with the students to discuss the difficulties and correct deficiencies in the work methods and specification in order to facilitate the approach of Practice II.
The ultimate goal of the course consists of the implementation of the proposed system in Prac-tice II, reaching, if possible, the real testing on the prototyping board. Thus, the emphasis is more on the development of the specification skills, simulation and debugging, and less on the generation of documentation. Since the number of students is not very high, teachers carry out a very close monitoring of their work.
At the end of the course the students are asked to hand in all the generated code and a brief re-port of the work done in Practice II, including the following information:
− Decisions made on the chosen architecture
− Differences with the proponed scheme and justification
− Difficulties encountered and their solution
− Degree of achievement of the final prototype
The final evaluation is based on the information in the report together with the results of a practical oral examination that takes place between a teacher and each lab Group, where the students must demonstrate:
− Their knowledge about the system developed
− The achievement grade in it
− Their proficiency in the use of tools and methodologies
The teacher also observes the ability of the students to communicate technical information, knowledge, justifications, etc. effectively and concisely and to answer the questions they are posed.
Technology of Semiconductors (TS 1)
The objective of this course is for students to acquire a basic knowledge of the most important technological processes applied to semiconductor materials used primarily in the field of nano- and microelectronics. Furthermore, the main effects that these techno-logical processes have on the optical and electrical properties will be explained as well as their application in optoelectronic devices.
DEVELOPMENT OF THE COURSE AND METHODOLOGY
For the development of the course there will be theory participative classes and discus-sion sessions and resolution practical problems. A collaborative teaching methodology will be used, promoting student-teacher interaction in tutoring and student-student, through discussions.
|
TOPIC |
Attendande hours |
|
I.- Introduction to semiconductor materials |
4 |
|
II. Manufacture of semiconductor materials |
2 |
|
III. Epitaxy of semiconductor materials III.1 Liquid Phase Epitaxy technique (LPE) III.2 MOCVD technique III.3 MBE technique |
6 |
|
IV. Doping techniques materials IV.1 Doping by diffusion IV.2 Doping by ion implantation |
4 |
|
V. Thermal Oxidation |
2 |
|
VI. Deposition in stage vapor (CVD) of insulating ma-terials |
2 |
|
VII. Metallization |
2 |
|
VIII. Chemical attacks wet and dry |
2 |
|
IX. Optical lithography and electron beam |
2 |
First exam
The score is divided in several parts:
- First part of the course (exercises) : 10%
- Second part of the course (exercises) : 15%
- Third part of the course (exercises) : 15%
- Written exam including all subjects: 60%
Extraordinary exam
A unique written exam including all subjects.
Engineering of Analogical and Digital Systems (SEAD 1)
The objective of this course is to introduce students in the techniques and software tools for the design of integrated circuits and electronic systems, with applications in information processing, communications and instrumentation. Students will learn to design:
• Analog submodules based on operational amplifiers (OPA).
• Digital subsystems from high-level descriptions, including the making of
o Control machines
o Arithmetic-logic data paths
In both cases, students learn how to use design tools and to make flow design.
Set 1. Introduction to digital systems
1.1 General Purpose Elements: Microprocessors and DSPs
1.2 Specific purpose elements: ASICs and FPGAs
1.2.1 Design flow
1.2.2 Languages for description of HW: VHDL
Set 2. Digital design
2.1 Combinational logic
2.2 Sequential logic
2.3 Arithmetic Circuits and Data Paths
2.4 Design at register transfer level (RTL)
Set 3: Timing in Synchronous Systems
3.1 Bias sources (skew) and fluctuation (jitter)
3.2 Clock Distribution Techniques
3.3 Synchronization with PLL
3.4 Signal integrity
Set 4. Ideal Operational Amplifier
4.1 Nonlinearities of the Operational Amplifier
4.2 Static constraints
4.3 Dynamic constraints
4.4 Noise
4.4 Stability
Set 5. Analog subsystems
5.1 Nonlinear circuits
5.2 Signal generators
5.3 References and Voltage Regulators
Set 6. Advanced issues
6.1 Realization of PCBs
6.2 Testability
6.3 Precompiled cores (memories, processors...)
6.4 Consumption
6.5 Electromagnetic compatibility
6.6 A/D and D/A converters
Evaluation in the ordinary examination periods will be based on the following parameters:
• Participation in forums and activities in the virtual environment (5%)
• Assistance at lessons (10%). Class attendance will be evaluated in accordance with the tasks proposed and performed during lessons hours.
• Proposed exercises, individual work or teamwork (45%)
• Final exam (40%). A minimum of 5.0 points should be obtained (otherwise the final grade will be ‘fail’, regardless of other qualifications). It will consist of a short question examination without books and some exercise to be developed.
In the extra exams the proposed exercise will weigh 50% at the expense of participation.
From the above, a continuous monitoring of the course it is important as well as the use of the forums, hours of tutoring and lessons to leave no remaining doubts that could impede a regular progress.
The study of the matter that will be indicated before undertaking any practical work or, of course, a follow-up examination is also fundamental.
Tools for Electronic Design (DASE 2)
This course aims to train students in the use of CAD tools for digital integrated circuit design, with special attention to the phases of synthesis, simulation, physical design and verification. On each topic will be a series of labs with professional tools and methodologies used in the electronics industry based on workflow standard cells.
Specific objectives:
- The student will understand and assess general combinatorial optimization methods that use CAD tools.
- The student will be familiar with the parameters that describe a standard cell library.
- The student will understand the algorithms involved in logic synthesis and technology equivalence of combinational and sequential circuits, and high-level synthesis. The student will be able to synthesize a circuit described in VHDL language using the tool "Synopsys Design Compiler" and characterize the synthesized circuit. The student will become familiar with the types of files provided by manufacturers of standard cells for synthesis.
- The student will understand the algorithms involved in various types of electronic circuit simulation. The student will be able to perform pre-synthesis simulations, post-synthesis and post-place & route using the tool "Modelsim". The student will become familiar with the types of delay models provided by manufacturers of standard cells for synthesis.
- The student will understand the algorithms involved in VLSI physical design phase: floorplanning, placement, routing and special routed. The student will be able to perform the physical design of a circuit synthesized using the tool "Cadence SOC Encounter", performing electrical and physical verification and characterization. The student will become familiar with the types of files provided by manufacturers of standard cells for physical design.
-
The student will understand the most common techniques for the verification of digital circuits. The student will become familiar with SystemVerilog and verification methodologies oriented at UVM 1.1. Students will be able to verify a circuit described in VHDL following the guidelines described by UVM 1.1.
The course consists of lectures and a series of associated practices will develop in pairs in the laboratory of Building B (B-043). Each pair is assigned a duty to choose between morning or afternoon. Each shift is three hours.
Agenda:
- Introduction (0.5 ECTS). Design methodologies. Standard cell libraries. Methods for general purpose combinatorial optimization. Laboratory: Analysis of a standard cell library.
- Synthesis (0.75 ECTS). Optimization and synthesis of combinational logic. Optimization of two-level logic. Optimization of multi-level logic. Sequential Logic Design: FSM synthesis. High-level synthesis. Task planning and allocation. Algorithms in CAD tools. Synthesis on FPGAs. Laboratory: Synthesis and characterization with Synopsys.
- Simulation (0.75 ECTS). Simulation types. Cell models. Delay Models. Formal Verification. Static timing analysis. Transistor-level simulation. Laboratory: Simulation with Modelsim.
- Physical Design (1 ECTS). Partition. Placing objects on 0-d. Placing objects in 1-d. Placing objects in 2-D. Global Connection. Channel Connection. Detailed Connection. Clock and Power Piping. Laboratory: Physical Design with Cadence SoC Encounter.
- Verification (1 ECTS). Introduction to verification. System level verification. Functional coverage. Statements (assertions). Introduction to SystemVerilog. UVM 1.1. Laboratory: system level verification with SystemVerilog UVM along the lines of 1.1.
Teaching methodology
The course is proposed as a mixture of lectures, which give a theoretical on algorithms and methodologies, plus a laboratory sessions where they put into practice the concepts learned. At the end of the internship students will submit a report to justify the work performed and results obtained. For each subject, the teacher will select two practice teams that will have to do a presentation with the results and participate in a discussion about their design decisions.
Partial multiple choice of items 4 and 5. 25%
Technical quality of the practices. 40%
Class participation and technical skills demonstrated in the laboratory sessions. 10%
Advanced Digital Architectures (ADA)
The subject of Advanced Digital Architectures is the last of the Masters’ Degree in relation to the most advanced matters in digital design. Its foundation subjects are those of the first quarter " Electronic Circuits and Systems Laboratory " and "Analog and Digital Electronic Systems".
In terms of content, in the first block is reviewed from processor-based digital architectures (memory systems, multiprocessor, parallelism, pipeline, etc.) to the more oriented to the calculation of algorithms (FPGAs, ASICs, etc.) which are less flexible but more efficient from the point of view of the application. In the second part, a set of techniques is explained that allows the performance of digital descriptions to be analyzed and optimized. Without loss of generality, in the second block, applications are oriented to the efficient implementation of algorithms for digital signal processing.
At the end, the student will have an overview of the latest digital architectures, and will be able to decide in each case (application) which is the best option; combining flexibility and computing power.
Educational objectives of the course
The main educational aims of the course are:
• To know the alternatives to implementing electronic designs: generic architectures and algorithm-oriented architectures.
• Value the design options of a particular application through the commitment to: efficiency, cost, power and flexibility.
• Use the basics of digital architecture design to improve the efficiency of processing: segmentation, parallelism, parallel processing, etc.
• Be able to optimize the performance of specific systems, using examples based on the field of digital signal processing.
To whom it is addressed?
It is intended for students of the Masters’ Degree in Electronic Systems Engineering who wish to and apply the techniques currently used in the design of complex systems at a deeper level.
The course is divided into the following blocks:
1.- Introduction (3h). Historical perspective of high-speed digital architectures. Quality metrics in the design: Cost, Functionality, Performance and Economy. Design techniques and acceleration systems: Pipelines, Parallelism, Caches, Virtual Memory.
2.- Generic architectures (12h). General purpose architectures. Caches and memory systems. Multiprocessors. Instruction sets RISC / CISC, vector instructions. Parallelism at instruction level, dynamic implementation. Introduction to static pipeline.
3.- Specific architectures (6h). Design technologies (FPGAs and ASICs), design of ASICs. Internal structure of the FPGAs, IP cores, embedded processors. FPGA-based design: major manufacturers and families of FPGAs, development tools, development boards.
4.- Design and optimization techniques (12h). Types of algorithm representation. Quantification: coefficients and signals. Stability. Optimization of quantified systems. Transformation of algorithms: pipeline, parallelism, retiming, loop winding and unwinding, systolic arrays.
TEACHING METHODOLOGY
Planned development of the subject
The course consists of two parts: In the first part (blocks 1-3) the technologies, alternatives and trends of today's digital systems are outlined, so it is mostly theoretical. In the second part, the techniques used to implement the systems are explained, so its character is eminently practical.
Concepts will be developed in the classes and issues that the student must be develop for the proper follow of the subject will be proposed. These issues will be directed to understanding and mastering the concepts of each topic.
In the practical classes a set of exercises based on the use of tools will be proposed in which students will apply the concepts explained in the lectures.
Scenarios that should be done individually or in groups will also be
proposed, as indicated in each case.
Any doubts that may arise, can be resolved either between the students themselves (which will be encouraged and valued), or by the teacher. Additionally, there is the possibility of personal tutoring with the teacher at the times indicated below.
Participation and initiative shown by the students in the different parts of the subject will be valued (see Evaluation section).
To increase the final grade, the interested students may submit a project on any of the topics of the course. It is necessary to pass the exam of the course to take this project into account.
Evaluation:
The evaluation will be based on the following parameters:
• Final exam (60%).
• Proposed tasks and exercises (30%).
• Attendance, participation and initiative (10%).
A minimum score of 5.0 must be obtained in the final exam (otherwise the grade will be ‘fail’ regardless of other qualifications).
From the above, a continuous monitoring of the course is of importance as is use of the forums, hours of tutoring and lessons, to leave no doubts remaining that could impede regular progress. The study of the subjet hat will be indicated before undertaking any practical work and, of course, a follow-up examination is also basic.
Intelligents Systems and Applications Laboratory (LSIA 2).
In this lab, students must develop a complete project including both practical and theoretical part. This project should focus on some of the subjects of the itinerary of intelligent systems and applications.
The proposed project this year is the development of a speech recognition system online, including the following:
• Collection and use of ATK
• Learning HTK tool
• Evaluation of the system with audio files
Teaching methodology
The teaching methodology is based on project based learning (PBL). By conducting a complete project, the student acquires the knowledge needed in the development of each of the modules
The evaluation will consist of the following:
• Developed: 50%
• Project presentation and defense: 25%
• Memory or project documentation made: 25%
Biomedical Imaging Systems (SIB 2)
Skills:
1. Analyze the techniques for the acquisition of biomedical imaging that show not only anatomy but also provide information on the operation or biological activity of a tissue or organ.
2. Analyze the molecular imaging techniques in detail, using different markers that allow molecules or genes to be identified.
3. Apply methodologies and smart processing algorithms that enable the relevant information to be obtained in each biomedical application.
Training activities and this relationship with skills:
The course is based on the delivery of lectures to acquire the aforementioned skills. Students complete the course with a final individual project to be presented publicly as part of the activities required to acquire the application skills and the secondary skills of documentation, communication and publication.
Coordination actions (if any):
Assessment and rating methods: Test exam (40% of the marks), Final Project (40% of the marks)
Pattern Recognition (REPO 1)
The main objective of this course is to give students some solid knowledge into the tech-niques of pattern recognition and optimization techniques, so will serve as support an appli-cation to a wide range of scientific disciplines and techniques.
More specifically, the skills aimed to develop among the students of the subject can be de-scribed as follows:
1. Apply the techniques of automatic classification and inference for decision making, in-formation extraction and design of complex systems.
2. Draw conclusions from experimental data, whatever the field in which the researcher works.
3. Optimize classifiers, being of interest to highlight the relationship between the choice of component density functions, the number of parameters needed so as to estimate what impels that choice and the amount of data available for a task, relevant feature selection and dimension reduction of experimental vectors.
4. Critically assess the performance of systems and select the best method of classifica-tion and learning of their experimental data.
5. Apply optimization techniques based on stochastic, heuristic and evolutionary meth-ods.
6. Integrate the knowledge from different sources optimally into management according to the incomplete information available: system status, temporal context, multimodal and personal.
The list of topics of the course deals mainly with contents related to machine learning, according to the following plan. Topic
Duration (hours)
Introduction and methodology. 6h
Bayes decision theory. 6h
Parametric estimation. 6h
Nonparametric estimation. 6h
Pre-processing and feature selection. 4h
Unsupervised Learning. 4h
SVM and CART. 2h
BN, ART and evolutionary methods. 6h
Optimization methods. 2h
Submission of papers. 2h
Teaching Methodology
Classes are using slides with explanations. At the end of the course, the students will present theirs works.
Students complete the course with a final individual character to be publicly submitted as part of efforts to acquire transferable skills of documentation, communication and publication.
The report must be in the typical format for IEEE conference papers (http://www.ieee.org/conferences_events/conferences/publishing/templates ....) to foster in students not only reading and interpretation of scientific and technical documents, but also the correct wording.
This final work must be eminently practical, and it should apply the techniques described in the course, preferably, to a problem that may be related to the activity of the student or professional researcher.
The final paper will constitute 70% of the final grade. There will be a written exam, which represents 30% of the final grade.
Analogical Systems (SEAN 2)
The overall objective of the course is that the student acquires a broad view of analog design aspects that allow both design analog circuits and systems, and understandelectronic equipment used in communications and instrumentation. Especially, the student will able to design with Operational Amplifiers and other analog integrated circuits as analog multipliers, linear voltage regulators and switched, VCOs, PLLs, etc.. Additional emphasis will be placed on the ability to assess the noise in the analog signal processing knowledge of the main limitations and consistent care when analog design.
The exact content of the program is adapted to the student profile To do this, at the beginning of course there is an analysis of the average profile and interests of reinforcement and intensification, indicated by attendees in the first class. In any case, the subject is divided into two parts, but by modulating the intensity of each subject based on the profile of students:
Part One: Concepts horizontal applications (~ 20 h)
• Sensors and Electronic signals in the interaction with the real world. Equivalent circuital real signal sources. Signal / noise ratio and management (conditioning) appropriate electronic signals as appropriate. Amplifiers required type and its limitations.
• Operational Amplifiers (AO) integrated. Basic structure and concrete according to the types and use of AO's current. Features, benefits and limitations of the AO's current. Basic Employment negative feedback (RN) in the AO's design. Easements circuital and practical design aspects.
• Use feedback advanced in design with AO's. Positive feedback and design possibilities offered. Frequency dependent feedback signal: RN instability or loss and compensation. Simultaneous feedback (positive and negative) and their use in analog design. New design aspects of Global Negative Feedback (RGN) and Balanced (GERD).
• ...
Second part: Getting more specific application (~ 20 h)
• Systems for handling weak signals. Types of electrical noise. AO's design for low noise performance in the system.
• Practical aspects of printed circuit (Seebeck effect, leak guard techniques, etc.). Noise reduction techniques in systems.
• Systems for analog signal processing. Integrated multiplier circuits. Features and employment according to the design requirements. Application Communications and Instrumentation: practical examples of current use circuits.
• Systems for signal acquisition and actuation. A / D Conversion High resolution: Oversampling and generators using "dither". Related noise reduction.
Data Acquisition Systems for PC. Integrated Circuits and Systems Drive (Smart Power IC's).
• Power amplifiers: design and thermal constraints.
• ...
2 components:
Personal work on a set of proposals for teachers
- Defined at mid-course
- Presentation type memory scientific article results
- 4 pages in two columns
- With title, abstract, memory, conclusions and bibliography
- With oral presentation in class
Examination
A set 2-3 with affordable problems developed in the classroom
Qualification
Personal work 30% + 70% Exam (mandatory pass both parts).
Titulación de Ingeniería de Telecomunicación
PLAN DE ESTUDIOS 94. La Ingeniería de telecomunicación es una carrera de cinco cursos de duración, estructurada en dos ciclos, según el plan de estudios actual en la UPM (Plan 94). En este enlace se encuentran el marco documental y legislativo del plan 94, y algunas definiciones útiles. El alumno deberá completar un total de 373,5 créditos para terminar la carrera, los cuales están divididos en asignaturas troncales y obligatorias, asignaturas optativas, y asignaturas de libre elección.
