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Advanced Digital Architectures (ADA)

Electronic document: 
Créditos Totales: 
4.0
Delivery dates: 
Second semester
Type of subject: 
Itinerario I3
Instructional Objectives: 

The subject of Advanced Digital Architectures is the last of the Masters’ Degree in relation to the most advanced matters in digital design. Its foundation subjects are those of the first quarter " Electronic Circuits and Systems Laboratory " and "Analog and Digital Electronic Systems".
In terms of content, in the first block is reviewed from processor-based digital architectures (memory systems, multiprocessor, parallelism, pipeline, etc.) to the more oriented to the calculation of algorithms (FPGAs, ASICs, etc.) which are less flexible but more efficient from the point of view of the application. In the second part, a set of techniques is explained that allows the performance of digital descriptions to be analyzed and optimized. Without loss of generality, in the second block, applications are oriented to the efficient implementation of algorithms for digital signal processing.
At the end, the student will have an overview of the latest digital architectures, and will be able to decide in each case (application) which is the best option; combining flexibility and computing power.

 

Educational objectives of the course

The main educational aims of the course are:
• To know the alternatives to implementing electronic designs: generic architectures and algorithm-oriented architectures.
• Value the design options of a particular application through the commitment to: efficiency, cost, power and flexibility.
• Use the basics of digital architecture design to improve the efficiency of processing: segmentation, parallelism, parallel processing, etc.
• Be able to optimize the performance of specific systems, using examples based on the field of digital signal processing.

To whom it is addressed?

It is intended for students of the Masters’ Degree in Electronic Systems Engineering who wish to and apply the techniques currently used in the design of complex systems at a deeper level.

Program: 

The course is divided into the following blocks:
1.- Introduction (3h). Historical perspective of high-speed digital architectures. Quality metrics in the design: Cost, Functionality, Performance and Economy. Design techniques and acceleration systems: Pipelines, Parallelism, Caches, Virtual Memory.
2.- Generic architectures (12h). General purpose architectures. Caches and memory systems. Multiprocessors. Instruction sets RISC / CISC, vector instructions. Parallelism at instruction level, dynamic implementation. Introduction to static pipeline.
3.- Specific architectures (6h). Design technologies (FPGAs and ASICs), design of ASICs. Internal structure of the FPGAs, IP cores, embedded processors. FPGA-based design: major manufacturers and families of FPGAs, development tools, development boards.
4.- Design and optimization techniques (12h). Types of algorithm representation. Quantification: coefficients and signals. Stability. Optimization of quantified systems. Transformation of algorithms: pipeline, parallelism, retiming, loop winding and unwinding, systolic arrays.

 

Review: 
TEACHING METHODOLOGY

Planned development of the subject
The course consists of two parts: In the first part (blocks 1-3) the technologies, alternatives and trends of today's digital systems are outlined, so it is mostly theoretical. In the second part, the techniques used to implement the systems are explained, so its character is eminently practical.
Concepts will be developed in the classes and issues that the student must be develop for the proper follow of the subject will be proposed. These issues will be directed to understanding and mastering the concepts of each topic.
In the practical classes a set of exercises based on the use of tools will be proposed in which students will apply the concepts explained in the lectures.
Scenarios that should be done individually or in groups will also be
proposed, as indicated in each case.
Any doubts that may arise, can be resolved either between the students themselves (which will be encouraged and valued), or by the teacher. Additionally, there is the possibility of personal tutoring with the teacher at the times indicated below.
Participation and initiative shown by the students in the different parts of the subject will be valued (see Evaluation section).
To increase the final grade, the interested students may submit a project on any of the topics of the course. It is necessary to pass the exam of the course to take this project into account.

 

Evaluation:

The evaluation will be based on the following parameters:
• Final exam (60%).
• Proposed tasks and exercises (30%).
• Attendance, participation and initiative (10%).
A minimum score of 5.0 must be obtained in the final exam (otherwise the grade will be ‘fail’ regardless of other qualifications).
From the above, a continuous monitoring of the course is of importance as is use of the forums, hours of tutoring and lessons, to leave no doubts remaining that could impede regular progress. The study of the subjet hat will be indicated before undertaking any practical work and, of course, a follow-up examination is also basic.

Faculty
Coordinator: 
Más Información
Subject code: 
93000718
Course Number which belongs within the qualification: 
1
Center impartation: 
ETSI Telecomunicación
Academic year of teaching: 
2013-2014
Bibliography: 

a) Recommended books:
- J. L. Hennessy, D. A. Patterson: “Computer Architecture: A Quantitative Approach”. 3rd Edition, Morgan Kaufmann Publishing Co., 2001.
- K. K. Parhi, “VLSI Digital Signal Processing Systems: Design and Implementation”, Wiley-Interscience, 1999.
- J. H. McClellan, C. S. Burrus, A. V. Oppenheim, T. W. Parks “Computer-Based Exercises for Signal Processing Using MATLAB (Matlab Curriculum Series)”, Prentice-Hall, 1997.
- J.M. Rabaey, A. Chandrakasan, B. Nikolic. "Circuitos Integrados Digitales", Pearson. 2004
b) Software:
- The Mathworks: Matlab, Simulink
- Synplicity: Synplify DSP
- Xilinx: ISE, System Generator, AccelDSP
- Altera: Quartus II Web Edition, Nios II Embedded Design Suite
- Mentor Graphics: ModelSim
c) Articles and additional literature, that will be indicated in the various topics of the course.