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Electronic Circuits (CELT)

Electronic document: 
Créditos Totales: 
3.0
Créditos de Laboratorio: 
3.0
Delivery dates: 
Primer semestre
Type of subject: 
Troncal/obligatoria
Website of the subject: 
http://celt.die.upm.es
Instructional Objectives: 

DESCRIPTION OF THE COURSE

The aim of this course is to develop a practice of a system

complex analog-digital electronic starting with a description and a

basic specifications.

The course begins with a theoretical classes where students receive information

on decomposition in said system modules, the methods

convenient for design and recommendations for installation on the plate

insertion. Furthermore, in the above indicated classes are more procedures

suitable for detecting performance problems and their solution to

Throughout the development of the circuit.

During the course of the course, students will use the means available

laboratory B-043 for the development of the practice, with the

help of teachers. Some classes are regularly taught theoretical

short duration in the laboratory.

Finally, the student will have to write a memory circuit technique

performed.

 

Program: 

SPECIFIC CONTENT

Block / Theme /

Chapter

Paragraph

Indicators

Related

two

Block 1:

Description

system

electronic

design

1.1 Description of the electronic system to be

developed throughout the course.

I1

1.2 Analysis of decomposition into modules.

I2

1.3 Details of each module.

I2

1.4 Interactions between.

I2

1.5 Basic specifications must meet the system

I1

Block 2:

Development

analog part

2.1 Distribution of food:

2.1.1 star topology power

2.1.2 Decoupling Capacitors

2.1.3 LEDs alert shorts

2.1.4 Efficient insertion of plates

I3

2.2 Rules General Assembly:

2.1.1 Power Operational Amplifiers

2.1.2 Transportation of signals through the circuit

2.1.3 Noise reduction: parasitic capacitances and

radiation

I3

2.3 Implementation of the modules:

2.3.1 Effects of component tolerances

Load 2.3.2 Effects of other stages

2.3.3 Effects of the real character

operational amplifiers: gain-width

Band and "slew rate".

I3

2.4 Search and Troubleshooting

I5, I6, I8


Page 9

SPECIFIC CONTENT

Block / Theme /

Chapter

Paragraph

Indicators

Related

two

Block 3:

Development

digital part

3.1 Power of the digital part:

3.1.1 Reduced switching noise

3.1.2 Decoupling Capacitors

I4

3.2 Generation of clock signals

3.2.1 The timer NE555

3.2.2 Obtaining defined flanks

I4

3.3 Implementation of the modules

3.3.1 Intended Use of integrated circuits

CMOS

3.3.2 Precautions sequential circuits:

times "setup" and "hold".

3.3.3 Synchronization signals

3.3.4 Logical status display: LEDs and displays

I4

3.4 Searching and Troubleshooting

I5, I6, I8

Block 4:

Preparation of

documentation

technique

4.1 Drafting of technical documentation

I9

4.2 Overview of measurements and theoretical diagrams

(Bode and timelines)

I7

4.3 Explanation of the differences between the data

calculated and measured.

I9

 

Review: 

Qualification Criteria

Students will be evaluated, by default, through ongoing evaluation. The

qualification of the subject will be as follows:

FINAL NOTE = 20% of the first oral evaluation MILESTONE + 60% Oral Assessment

final circuit + 20% Development of improvements.

Laboratory evaluation is performed by controlling knowledge oral

on practical design, functioning and adaptation to the specifications,

knowledge of the use of laboratory equipment and writing memory

written.

In compliance with the Regulatory Evaluation of the Technical University of

Madrid, students who wish to be evaluated by a single final exam

provided that they inform the Director of the Department of Engineering

Electronics on application in the register of the School

Telecommunication Engineering. This request can be made ​​until the day

prior to the official announcement of the final exam. For eligible for

final exam mode, the score will be obtained as follows:

FINAL NOTE = 80% oral evaluation of the complete system (memory, knowledge

on the design and operation of the practice) + 20% Improvements. DATE:

Week 15 of the course. PLACE: Laboratory B-043

 

Faculty
Más Información
Subject code: 
95000025
Course Number which belongs within the qualification: 
3
Previous Knowledge: 

Circuit Analysis

• Introduction to Electronics

• Digital Electronics

• Analog Electronics

 

 

Academic year of teaching: 
2012-2013
Bibliography: 

"Practical aspects of design and extent Laboratories

Electronics "(2nd ed) (ISBN 84-7402-297-5), Javier

Ferreiros Lopez, Javier Macias Guarasa, Juan Manuel

Montero Martínez, Félix Moreno González, Juan Alberto

Susín Munoz, Elena Palazuelos Cagigas Sira, Julio Pastor

Mendoza, Ruben Hernandez San Segundo, Maria Jesus

Carbayo Ledesma. Publications Department ETSIT

"Electronic Circuits: Analysis, Design and Simulation",

Norbert R. Malik, Prentice-Hall, 1996.

"Design with Operational Amplifiers and Analog

Integrated Circuits ", 3rd edition Sergio Franco, McGraw-Hill,

2002

 

Tribunal