It is my pleasure to announce the next seminar on Advances on Electronic Systems Engineering that will be at 5pm, Salón de Grados Building A. The speaker is Dr. Ruzica Jevtic, from UC Berkeley, USA. Details on the talk are provided next. As usually, you all are welcome.
Title: Designing energy-efficient many-core processor: How to fight process variations
Abstract: Traditional processors are designed to ensure error-free operations under
worst-case conditions. Consequently, these designs cannot exploit the opportunities
for energy and performance improvement when conditions are favorable. This talk will
focus on new highly parallel many-core architectures that are designed to dynamically
tolerate variability in a projected future sub-nanometer process at very low supply
voltages and hence, attain large gains in energy efficiency. Several specific architecture
elements are embedded in the processor so as to achieve this: hardware delay and
performance monitors are embedded in logic so that the process variability can be
observed in-situ; dynamic voltage and frequency scaling technique is used to achieve
optimal energy point while maintaining desired performance; an unconventional
power supply scheme is synchronized with the clock generation scheme to enable
maximum energy efficiency. The expected energy savings are an order of magnitude
larger when compared to traditional energy optimization techniques.
Bio: Ruzica Jevtic received the B.S. degree in Electrical Engineering from the University
of Belgrade, Serbia in 2004 and Ph.D degree in Electrical Engineering with European
PhD mention from the Technical University of Madrid, Spain, in 2009. Her PhD work is
oriented towards CAD tools for high-level modeling, power estimation, measurements
and architecture design for high-speed computational systems in FPGAs. She is
currently working as a postdoctoral researcher at the Department of Electrical
Engineering and Computer Sciences, University of California, Berkeley on energy
efficient microprocessor design. In particular, her research interest is in design of
switched capacitor circuits for DVFS on many-core processors. She is a recipient of FP7
Marie Curie International Outgoing Fellowship.
